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[测试机资料] Teradyne UFLEX SB6G模块培训材料 [pdf] [复制链接]

Rank: 8Rank: 8

发表于 2012-9-16 10:12:10 |显示全部楼层
SB6G_StudentManual(instr).pdf (3.52 MB, 下载次数: 1003)

SB6G是用来测试高速串口通讯的模块,高速串口通讯是比较新的技术和协议,大家看看吧

• SB6G Terminology & Overview
– Serial Bus Basics
• High Speed Serial Bus
Characteristics
• What is SerDes?
• SerDes Timing & Data Uncertainty
• SerDes Embedded Clock
• 8b10b Encoding
• Serial Bus Test Requirements
– SB6G Instrument Features
• Basic Features
• SB6G Drive Features
• SB6G Receive Features
• SB6G Summary
– SB6G Basics & Instrument Review
• SB6G Programming and Theory
Connections, Levels, and PPMU
– Test Program Workbook with SB6G
• DUT Tx/Rx Differential Connections
• SB6G Pin Map
• SB6G Channel Map
• SB6G Driver/Receiver Theory
• SB6G Pin Levels
• TheHdw.Serial.Pins: Differential
Levels
– SB6G PinMap/ChanMap/Levels:
Review/Lab 1
– SB6G Pin PMU
• DUT Rx & Tx pins
• SB6G PPMU Ranges
• PPMU Continuity Test Instance
• PPMU VBT Language Statements
• PPMU Debug Display
– SB6G PPMU: Review/Lab 2
• SB6G Programming and Theory:
Patterns, Timing, Functional Tests, and
Sig Gen
– SB6G Pattern Files & Pattern Sets Sheet
• Vector & Capture Memory DUT Rx/Tx
• SB6G Patterns: Statements/Data
• Drive to Midband
• SB6G Drive/Receive Pattern Examples
• IG-XL Pattern Compiler
• PatternTool Debug Display
• HSD Pattern: ISL Mode
• HSD: Start Rx/TX Patterns
• SB6G Pseudo-Random Bit Sequence
• Serial Pattern Sets Sheet
– SB6G Pattern Files & Pattern Sets:
Review/Lab 3
– SB6G Serial Timing
• SB6G Timing: DUT Rx/Tx
• SB6G Receive Align Trigger
• RAT: Clock Data Recovery (CDR)
• RAT: 10 Bit Align & 20 Bit Match
• SB6G Serial Timing Sheet
• Test Instances Sheet
– SB6G Serial Timing: Review/Lab 4
– SB6G Functional Testing
• SB6G Functional Tests: Using ISL
• SB6G Functional Tests: Using Async
• VBT Test Instances
• Starting HSD and SB6G Patterns
• HRAM Serial Language
• Capture Memory Serial Language
• Serial Channel Debug Display
– SB6G Capture Memory
Demonstration
– SB6G Functional Test: Review/Lab 5
– SB6G Signature Generation
• Nondeterministic Issues
• Signature Generation
• Symbol Map Memory
• Signature Generator
• Signature Generation Programming
• Signature Generation Debug: Serial
Capture Tool
– Signature Generation: Review/Lab 6
• SB6G Programming and Theory:
Jitter Insertion, and Jitter/Eye
Measure Tests
– Jitter Insertion
• SB6G Driver: Jitter Insertion
• Jitter Insertion Guidelines
• Jitter Insertion Sheet
– Amplitude and Frequency
– Master Period
• Jitter Insertion Tests
• Jitter Insertion VBT
– Jitter Insertion Test: Review/Lab7
– Jitter & Eye Measure Testing
• Serial Bus Test Challenges
• Jitter Measure Hardware
• What are Jitter/Jitter Components?
• Jitter Measurements
• Eye Measurements
• Jitter & Eye Width Measure Test
Programming
– Levels
– Jitter Sheet: Measurement
– VBT Setup
– runDSP
– Limits
• Jitter Tool
– Jitter/Eye Measure Test: Review/Lab 8
– Appendix A: DIB Interface
– Appendix B: DIB 8b10b Encoding
Standard
– Appendix C: PatGen Start Scenario
– Appendix D: Jitter Tool User Guide

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